1. Field
The following description relates to delay-locked loop (DLL) operation mode control. Additionally, the following description relates to a DLL operation mode control circuit configured to determine a mode of a DLL circuit block chosen from standby mode and normal operation mode, according to clock frequency or operational status of a display driver IC (DDI), and a corresponding method.
2. Description of Related Art
Increasing clock frequency is a technique that is utilized to further improve operation speed of semiconductor-based integrated circuits (ICs). However, increasing clock frequency increases power consumption for the IC because it is necessary to drive a delay-locked loop (DLL) circuit to change the clock frequency. Driving a DLL circuit uses additional power, which increases power consumption for the IC as a whole. Hence, research is being actively conducted to find ways to reduce power consumption by the DLL circuits, to allow increased clock frequency while minimizing power consumption.
The preceding issues are involved with the increased use of miniaturized display products which use a display driver IC (DDI) with lower power consumption. That is, since DDI technology is often implemented in mobile products such as mobile phones or portable media players (PMPs), lower power consumption is closely related to increasing use time of the mobile devices. Such mobile devices generally operate as portable devices by using batteries that store a finite amount of energy. Hence, if less power is consumed by the device, the energy in the battery is depleted more slowly and the device is able to function for a longer period of time. Additionally, reducing power consumption is generally desirable due to the cost of replacement batteries and/or the cost of electrical power. Due to these considerations, continuous efforts are underway to reduce power consumption for employing a DDI for panel use, such as in a liquid crystal display (LCD) screen, a plasma display panel (PDP), a TV or a laptop computer.
One way to reduce power consumption at a DDI is to control the driving status of the DLL circuit. That is, it is possible to reduce power consumption by the DLL circuit driving the DDI, by causing the DLL circuit to switch between normal mode and standby mode depending on the driving status of the DDI. Thus, in such an approach, the increased clock frequency provided by the DLL is only employed in situations where it is beneficial to do so.
An example way to control driving status of the DLL circuit block for use with DDI is presented below with reference to FIGS. 1 and 2.
FIG. 1 illustrates an example of a circuit where an external signal is used. The control circuit 10 illustrated in FIG. 1 is configured to switch a DLL circuit block 20 to standby mode by externally applying a standby enable signal to the DLL circuit block 20.
To that purpose, the DLL circuit block 20 includes a controller 14 that applies a standby enable (stb_en) signal to the DLL circuit block 20 upon activation of an enable signal apply pin 12 communicatively connected to the controller 14.
In one example, the standby enable signal apply pin 12 is implemented as a button or a switch. The DLL circuit block 20 also includes a comparing unit which receives CLKP and CLKN signals, a phase frequency detector, a charge pump and a voltage controlled delayer.
As explained above, the approach illustrated in FIG. 1 enables a user to switch a driving mode of the DLL circuit block 20 as intended, because the user is able to put the DLL circuit block 20 into standby mode by activating the standby enable signal apply pin 12.
However, the approach of FIG. 1 using standby enable signal apply pin 12 leads to increased cost due to its requirement for the standby enable signal apply pin 12 and related circuits. Furthermore, since the user himself or herself directly activates the standby enable signal apply pin 12, precise timing on the user's part is required when switching from normal to standby mode. When the standby enable signal is applied too slowly when switching to standby mode, unnecessary power consumption occurs. Further, a user may arbitrarily apply a standby enable signal during operation in normal mode. In such a case, the DLL circuit block 20 does not operate normally because the standby enable signal forces it into standby mode, even when operating in such a mode is not appropriate or beneficial.
Another example of a method for controlling driving status of the DLL circuit block operates by detecting an operational status of CLKP/N, which is the output value of the DDI. Such an approach is presented below with reference to FIG. 2.
FIG. 2 illustrates a DLL circuit block 40 to which the CLKP/N signal, which is the output value from the DDI, is inputted.
A level detecting unit 50 is connected to an input end of the DLL circuit block 40. In the example of FIG. 2, the level detecting unit 50 is connected to a common terminal (n) to which the CLKP/N signal is applied.
The level detecting unit 50 includes a comparator 52.
The comparator 52 is configured so that a pull-up resistor (R3) and an internal voltage (VDDI) terminal are connected to a non-inverting terminal (+) of the comparator 52, and a reference voltage (Vref) is applied to an inverting terminal (−) of the comparator 52.
The comparator 52 outputs a standby enable signal (stb_en) only when the common terminal voltage (Vcom) received at the non-inverting terminal (+) exceeds the reference voltage (Vref). That is, because the non-inverting terminal (+) acquires a pull-up state by the internal voltage (VDDI) when the CLKP/N signal reaches a high impedance state, the common terminal voltage (Vcom) exceeds the reference voltage (Vref) in such a situation.
As explained above, FIG. 2 illustrates an example where the DLL circuit block 40 is automatically switched to standby mode as a result of detecting that the CLKP/N signal is in a high impedance state, without an external signal to invoke the switching process.
However, a circuit construction such as the one illustrated in FIG. 2 continues to have shortcomings. These shortcomings are explained below with reference to FIGS. 3A and 3B.
FIG. 3A illustrates a standby mode interval and a normal mode interval of the circuit illustrated in FIG. 2, and FIG. 3B illustrates operation areas of the standby mode and normal operation mode of the circuit illustrated in FIG. 2.
Referring to FIG. 3A, the normal mode interval (c) spans from time point (a) at which the output from the DDI, that is, the CLKP/N signal, changes from the high impedance state until time point (b) at which the CLKP/N signal changes back to high impedance state, and the rest intervals (d and e) are the standby mode intervals. Thus, the normal mode interval (c) corresponds to when the common terminal voltage (Vcom) is smaller than the reference voltage (Vref) so that the DLL circuit block is in its normal operation range.
However, transitioning between standby and normal mode requires time. For example, a predetermined time is required for the clock circuit of the DDI associated with a DLL as illustrated in FIG. 2 to reach a normal frequency during switching from standby mode to normal mode, such as from (d) to (c), or switching from normal mode to standby mode, such as from (c) to (e).
Thus, based on the transition time issue discussed above, there is an interval spanning the mode switching time. In such an interval, the DLL circuit block 40 cannot operate normally, because during the transition time it is not actually in a normal operational mode. That is, the DLL circuit block 40 also has to be switched to standby mode when the clock frequency of CLKP/N is smaller than the normal operation frequency of the DLL circuit block, so that the DLL circuit block is not relied upon for normal operation when it is in a transition between normal and standby mode.
However, since the approach of FIG. 2 is limited only to an occasion when the common terminal voltage (Vcom) is larger than the reference voltage (Vref), in practice, there is a low frequency domain in the normal mode interval where the DLL circuit block 40 cannot operate normally.
FIG. 3B illustrates the frequency domains (f′ and f″) where the DLL circuit block cannot operate. In these frequency domains (f′ and f″) the DLL circuit block is also under transition. Referring to FIG. 3B, although included in the normal mode interval (c), the intervals (g′ and g″) corresponding to frequency domains (f′ and f″) are intervals when the DLL circuit block 40 can malfunction.
That is, referring to FIG. 2, although the DLL circuit block 40 has the normal mode interval (c), due to frequency domains (f and f″) where the DLL circuit block 40 cannot operate normally due to being in transition, the normal mode interval (c) also includes the intervals (g′ and g″) where the DLL circuit block cannot operate normally.
Hence, FIG. 2 also illustrates the issue in which the DLL circuit block 40, which is designed to operate on standby mode in certain intervals, cannot easily switch to standby mode due to the presence of inoperable frequency domains, as explained above.
Accordingly, the related circuit configuration of FIG. 2 has the problem of unstable operation of a DLL circuit block.